A clock recovery phase-locked loop circuit is employed, for example, in digital audio equipment to generate clock signals useful for extracting audio data from incoming audio signals, and clocking digital-to-analog converters to generate output audio signals after processing. In such and other applications, the incoming signals may be encoded at different and wide ranging sampling rates, presenting stability and/or response time problems for a clock recovery phase-locked loop circuit generating synchronized clock signals from such incoming signals.
There are several digital audio standards in existence. Audio compact disks (CDs) commonly use a sampling rate of 44.1 Khz. Other digital audio standards use sampling rates of 32 Khz, 48 Khz, and 96 Khz. To provide optimal stability and response time, it is desirable to tune a clock recovery phase-locked loop circuit to the sampling rate, or a center frequency within a narrow range including the sampling rate, of the incoming audio signal, so as to operate the clock recovery phase-locked loop circuit in a linear region having wide dynamic output range. Accordingly, in digital audio equipment receiving incoming data signals of such wide ranging sampling rates, a tunable clock recovery phase-locked loop circuit is useful, and a self-tuning clock recovery phase-locked loop circuit is particularly useful.
Tuning a phase-locked loop circuit also commonly requires a stable reference or tuning clock. In digital systems, the system clock is commonly used for this purpose. Accordingly, since system clock frequencies may vary substantially from system to system, it is useful for clock recovery phase-locked loop circuits included in commercially standard integrated circuit devices, to be readily and reliably tunable when used in various systems operating at different system clock frequencies. It is also useful for such clock recovery phase-locked loop circuits to accommodate process variations in their manufacture, and temperature effects in their operation.